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1 p/n:pm0722 rev. 0.7, jul. 12, 2001 mx29lv040 advance information 4m-bit [512k x 8] cmos single voltage 3v only equal sector flash memory then resumes the erase. ? status reply - data polling & toggle bit for detection of program and erase operation completion. ? sector protection - hardware method to disable any combination of sectors from program or erase operations - any combination of sectors can be erased with erase suspend/resume function. - tempoary sector unprotect allows code changes in previously locked sectors. ? 100,000 minimum erase/program cycles ? latch-up protected to 100ma from -1v to vcc+1v ? low vcc write inhibit is equal to or less than 2.3v ? package type: - 32-pin plcc - 32-pin tsop ? compatibility with jedec standard - pinout and software compatible with single-power supply flash features ? extended single - supply voltage range 2.7v to 3.6v ? 524,288 x 8 only ? single power supply operation - 3.0v only operation for read, erase and program operation ? fast access time: 55r/70/90ns ? low power consumption - 20ma maximum active current - 0.2ua typical standby current ? command register architecture - 8 equal sector of 64k-byte each - byte programming (9us typical) - sector erase (sector structure 64k-byte x8) ? auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability. - automatically program and verify data at specified address ? erase suspend/erase resume - suspends sector erase operation to read data from, or program data to, any sector that is not being erased, general description the mx29lv040 is a 4-mega bit flash memory orga- nized as 512k bytes of 8 bits. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx29lv040 is packaged in 32-pin plcc and tsop. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx29lv040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx29lv040 has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx29lv040 uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum eprom compatibility. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. the mx29lv040 uses a 2.7v~3.6v vcc supply to perform the high reliability erase and auto program/ erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v.
2 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 pin configurations 32 plcc 32 tsop (standard type) (8mm x 20mm) symbol pin name a0~a18 address input q0~q7 data input/output ce chip enable input we write enable input oe output enable input gnd ground pin vcc +3.0v single power supply pin description sector a18 a17 a16 address range sa0 0 0 0 00000h-0ffffh sa1 0 0 1 10000h-1ffffh sa2 0 1 0 20000h-2ffffh sa3 0 1 1 30000h-3ffffh sa4 1 0 0 40000h-4ffffh sa5 1 0 1 50000h-5ffffh sa6 1 1 0 60000h-6ffffh sa7 1 1 1 70000h-7ffffh note:all sectors are 64 kbytes in size. sector structure table 1. mx29lv040 sector address table 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we a17 mx29lv040 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29lv040
3 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx29lv040 flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a18 ce oe we
4 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 automatic programming the mx29lv040 is byte programmable using the auto- matic programming algorithm. the automatic program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. the typical chip programming time at room temperature of the mx29lv040 is less than 10 seconds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 11 second. the automatic erase algorithm automatically programs the entire array prior to electri- cal erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the mx29lv040 is sector(s) erasable using mxic's auto sector erase algorithm. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are controlled internally within the de- vice. an erase operation can erase one sector, multiple sectors, or the entire device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and a0h) and a program command (program data and address). the device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. the device provides an unlock bypass mode with faster programming. only two write cycles are needed to pro- gram a word or byte, instead of four. a status bit similar to data polling and a status bit toggling between con- secutive read cycles, provide feedback to the user as to the status of the programming operation. refer to write operation status-table6, for more information on these status bits. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the erasing operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we or ce, whichever hap- pens first. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx29lv040 electri- cally erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set. automatic select the automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on q7~q0. this mode is mainly adapted for programming equipment on the de- vice to be programmed with its programming algorithm. when programming by high voltage method, automatic select mode requires vid (11.5v to 12.5v) on address pin a9 and other address pin a6, a1, and a0 as referring to table 2. in addition, to access the automatic select codes in-system, the host can issue the automatic se
5 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 lect command through the command register without requiring vid, as shown in table 3. to verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest or- der address bit (see table 1 and table 2). the rest of address bits, as shown in table3, are don't care. once all necessary bits have been set as required, the pro- gramming equipment may read the corresponding iden- tifier code on q7~q0. a18 a15 a9 a8 a6 a5 a1 a0 description ce oe we | | | | q7~q0 a16 a10 a7 a2 read silicon id l l h x x vid x l x l l c2h manfacturer code read silicon id l l h x x vid x l x l h 4fh 01h sector protection l l h sa x vid x l x h l (protected) verification 00h (unprotected) table 2. mx29lv040 automatic select mode operation note:sa=sector address, x=don't care, l=logic low, h=logic high
6 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read manufacturer id 4 555h aah 2aah 55h 555h 90h x00h c2h read silicon id 4 555h aah 2aah 55h 555h 90h x01h 4fh sector protect 4 555h aah 2aah 55h 555h 90h (sa) 00h verify x02h 01h porgram 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h table 3. mx29lv040 command definitions note: 1. adi = address of device identifier; a1=0, a0 = 0 for manufacturer code,a1=0, a0 = 1 for device code. a2-a18=do not care. (refer to table 2) ddi = data of device identifier : c2h for manufacture code, 4fh for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2.pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector to be erased. 3. for sector protect verify operation:if read out data is 01h, it means the sector has been protected. if read out data is 00 h, it means the sector is still not being protected.
7 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 address description ce oe we a18 a15 a9 a8 a6 a5 a1 a0 q0~q7 a16 a10 a7 a2 read l l h ain dout write l h l ain din(3) reset x x x x high z output disable l h h x high z standby vcc 0.3v x x x high z sector protect l h l sa x x x l x h l x chip unprotect l h l x x x x h x h l x sector protection verify l l h sa x vid x l x h l code(5) table 4. mx29lv040 bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 3. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 3 for valid data-in during a write operation. 4. x can be vil or vih, l=logic low=vil, h=logic high=vih. 5. code=00h/xx00h means unprotected. code=01h/xx01h means protected. 6. a18~a13=sector address for sector protect. sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 3 defines the valid register command
8 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 requirements for reading array data to read array data from the outputs, the system must drive the ce and oe pins to vil. ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory contect occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device or erase sectors of memory , the sysytem must drive we and ce to vil, and oe to vih. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a byte, instead of four. the "byte program command sequence" section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors , or the entire device. table indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. the "writing specific address and data commands or sequences into the command register initiates device operations. table 3 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal reqister (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence section for more information. icc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. standby mode when the sysytem is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe input. the device enters the cmos standby mode when the ce pin is both held at vcc 0.3v. (note that this is a more restricted voltage range than vih.) if ce is held at vih, but not within vcc 0.3v, the device will be in the standby mode, but the standby currect will be greater. the device requires standard access time (tce) for read access when the device is in either of these standby modes, before itis ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. icc3 in the dc characteristicstable represents the standby current specification. output disable with the oe input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state.
9 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage(vid). however, multiplexing high voltage onto address lines is not generally desired system de- sign practice. the mx29lv040 contains a silicon-id-read operation to supple traditional prom programming methodology. the operation is initiated by writing the read silicon id command sequence into the command register. fol- lowing the command write, a read cycle with a1=vil, a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of 4fh for mx29lv040. set-up automatic chip/sector erase commands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cy- cles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 6), indicating the erase operation exceed internal timing limit. the automatic erase begins on the rising edge of the last we or ce pulse, whichever happens first in the command sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two con- secutive read cycles, at which time the device returns to the read mode. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) manufacture code vil vil x 1 0 0 0 0 1 0 c2h device code vih vil 0 1 0 0 1 1 1 1 4fh sector protection verification vil vih 0 0 0 0 0 0 0 0 00h (unprotected) table 5. expanded silicon id code
10 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see rase suspend/erase resume commands for more infor-mation on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the autoselect mode. see the "reset command" section, next. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be-fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins,however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an silicon id read command sequence. once in the silicon id read mode, the reset command must be written to return to reading array data (also applies to silicon id read during erase suspend). if q5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). sector erase commands the automatic sector erase does not require the de- vice to be entirely pre-programmed prior to executing the automatic sector erase set-up command and au- tomatic sector erase command. upon executing the automatic sector erase command, the device will auto- matically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "un- lock" write cycles. these are followed by writing the set-up command 80h. two more "unlock" write cycles are then followed by the sector erase command 30h. the sector address is latched on the falling edge of we or ce, whichever happens later, while the command(data) is latched on the rising edge of we or ce, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we or ce, whichever happens later. each successive sector load cycle started by the falling edge of we or ce, whichever happens later must begin within 50us from the rising edge of the preceding we or ce, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode.
11 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 status q7 q6 q5 q3 q2 (note1) (note2) byte program in auto program algorithm q7 toggle 0 n/a no toggle auto erase algorithm 0 toggle 0 1 toggle erase suspend read 1 no 0 n/a toggle (erase suspended sector) toggle in progress erase suspended mode erase suspend read data data data data data (non-erase suspended sector) erase suspend program q7 toggle 0 n/a n/a byte program in auto program algorithm q7 toggle 1 n/a no toggle exceeded time limits auto erase algorithm 0 toggle 1 1 toggle erase suspend program q7 toggle 1 n/a n/a table 6. write operation status note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information.
12 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 100us to suspend the erase operations. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after this command has been ex- ecuted, the command register will initiate erase suspend mode. the state machine will return to read mode auto- matically after suspend is ready. at this time, state ma- chine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. automatic program commands to initiate automatic program mode, a three-cycle com- mand sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic pro- gram command a0h. once the automatic program command is initiated, the next we pulse causes a transition to an active program- ming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we or ce, whichever happens first. the rising edge of we or ce, whichever happens first, also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. the device provides q2, q3, q5, q6, q7 to determine the status of a write operation. if the program operation was unsuccessful, the data on q5 is "1"(see table 7), indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two con- secutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode(no program verify command is required). word/byte program command sequence the device programs one byte of data for each program operation. the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 3 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6, or ry/by. see "write operation status" for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operat ion. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may halt the operation and set q5 to "1" , or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1".
13 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 write operstion status the device provides several bits to determine the sta- tus of a write operation: q2, q3, q5, q6 and q7. table 10 and the following subsections describe the functions of these bits. q7 and q6 each offer a method for deter- mining whether a program or erase operation is com- plete or in progress. these three bits are discussed first. q7: data polling the data polling bit, q7, indicates to the host sys-tem whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing er ase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. if a pro- gram address falls within a protected sector, data poll- ing on q7 is active for approximately 1 us, then the de- vice returns to reading array data. during the automatic erase algorithm, data polling pro- duces a "0" on q7. when the automatic erase algo- rithm is complete, or if the device enters the erase sus- pend mode, data polling produces a "1" on q7. this is analogous to the complement/true datum out-put de- scribed for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement, or "0". the system must provide an address within any of the sec- tors selected for erasure to read valid status information on q7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data polling on q7 is active for approximately 100 us, then the device returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchr onously with q0-q6 while output en- able (oe) is asserted low. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we or ce, whichever happens first, in the command sequence(prior to the pro- gram or erase operation), and during the sector time- out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to con- trol the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles and returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase sus- pended. when the device is actively erasing (that is, the automatic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to determine which sectors are erasing or erase-sus- pended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 6 shows the outputs for toggle bit i on q6.
14 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively eraseing (that is, the automatic erase alorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we or ce, whichever happens first, in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 6 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfuly completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alterna- tively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. q5 exceeded timing limits q5 will indicate if the program or erase time has ex- ceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not successfully completed. data polling and toggle bit are the only operating functions of the device under this condition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). the time-out condition will not appear if a user tries to program a non blank location without erasing. please note that this is not a device failure condition since the device was incorrectly used. q3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase com- mand sequence.
15 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 power-up sequence the mx29lv040 powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences. sector protection the mx29lv040 features hardware sector protection. this feature will disable both program and erase opera- tions for these sectors protected. to activate this mode, the programming equipment must force vid on address pin a9 and oe (suggest vid = 12v). programming of the protection circuitry begins on the falling edge of the we pulse and is terminated on the rising edge. please refer to sector protect algorithm and waveform. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih). when a1=vih, a0=vil, a6=vil, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will produce 00h for the unprotected sector. in this mode, the addresses,except for a1, are don't care. address locations with a1 = vil are reserved to read manufacturer and device codes.(read silicon id) it is also possible to determine if the sector is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the com- mand has been accepted, the system software should check the status of q3 prior to and following each sub- sequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the mx29lv040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. the device also incorpo- rates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. pow er supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd.
16 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 chip unprotect the mx29lv040 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih. refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we pulse and is terminated on the rising edge. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed.
17 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe, and reset (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9, oe, and reset is -0.5 v. during voltage transitions, a9, oe, and reset may overshoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc input volt- age on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum rat-ings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40 c to +85 c extended (e) devices ambient temperature (t a ). . . . . . . . . -55 c to +125 c v cc supply voltages v cc for regulated voltage range . . . . . +3.0 v to 3.6 v v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
18 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 table 8. capacitance ta = 25 o c, f = 1.0 mhz symbol p arameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed. 3. automatic sleep mode enable the low power mode when addresses remain stable for tacc +30ns. read operation table 9. dc characteristics ta = 0 o c to 70 o c, vcc = 2.7v to 3.6v symbol p arameter min. typ max. unit conditions ili input leakage current 1 ua vin = vss to vcc ilit a9 input leakage current 35 ua vcc=vcc max; a9=12.5v ilo output leakage current 1 ua vout = vss to vcc, vcc=vcc max icc1 vcc active read currect 7 12 ma ce=vil, oe=vih @5mhz 2 4 ma @1mhz icc2 vcc active write currect 15 30 ma ce=vil, oe=vih icc3 vcc standby currect 0.2 5 ua ce;vcc 0.3v icc4 vcc standby currect 0.2 5 ua ce; vcc 0.3v during reset icc5 automative sleep mode 0.2 5 ua vih=vcc 0.3v;vil=vss 0.3v vil input low voltage(note 1) -0.5 0.8 v vih input high voltage 0.7xvcc vcc+ 0.3 v vid voltage for auto select and temporary 11.5 12.5 v vcc=3.3v sector unprotect vol output low voltage 0.45 v iol = 4.0ma, vcc= vcc min voh1 output high voltage(ttl) 0.85xvcc ioh = - 2ma, vcc=vcc min voh2 output high voltage vcc-0.4 ioh = -100ua, vcc min (cmos) vlko low vcc lock-out 2.3 2.5 v voltage
19 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 29l v040-55r 29l v040-70 29l v040-90 symbol p arameter min. max. min. max. min. max. unit conditions trc read cycle time (note 1) 55 70 90 ns tacc address to output delay 55 70 90 ns ce=oe=vil tce ce to output delay 55 70 90 ns oe=vil toe oe to output delay 30 30 35 ns ce=vil tdf oe high to output float (note1) 0 25 0 25 0 30 ns ce=vil toeh output enable read 0 0 0 ns hold time toggle and 10 10 10 ns data polling toh address to output hold 0 0 0 ns ce=oe=vil note: 1. not 100% tested. 2. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0v/3.0v. ? input rise and fall times is equal to or less than 5ns. ? output load: 1 ttl gate + 100pf (including scope and jig), for 29lv040-90. 1 ttl gate + 30pf (including scope and jig) for 29lv040-70 & 29lv040-55r. ? reference levels for measuring timing: 1.5v. ac characteristics ta = -40 o c to 85 o c, vcc = 2.7v~3.6v (ta = 0 o c to 70 o c, vcc = 3.3v 5% for mx29lv040-55r) table 11. read operations
20 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 1. switching test circuits figure 2. switching test waveforms test points 3.0v 0v ac testing: inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. output 1.5v 1.5v input device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=100pf including jig capacitance cl=30pf for mx29lv040-70 & mx29lv040-55r
21 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 3. read timing waveforms addresses ce oe tacc we vih vil vih vil vih vil vih vil voh vol vih vil high z high z data valid toe toeh tdf tce tacc trc outputs reset toh add valid
22 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 ac characteristics ta = -40 o c to 85 o c, vcc = 2.7v~3.6v (ta = 0 o c to 70 o c, vcc = 3.3v 5% for mx29lv040-55r) table 11. erase/program operations 29lv040-55r 29lv040-70 29lv040-90 symbol parameter min. max. min. max. min. max. unit twc write cycle time (note 1) 55 70 90 ns tas address setup time 0 0 0 ns tah address hold time 45 45 45 ns tds data setup time 35 35 45 ns tdh data hold time 0 0 0 ns toes output enable setup time 0 0 0 ns tghwl read recovery time before write 0 0 0 ns (oe high to we low) tcs ce setup time 0 0 0 ns tch ce hold time 0 0 0 ns twp write pulse width 35 35 35 ns twph write pulse width high 30 30 30 ns twhwh1 programming operation (note 2) 9(typ.) 9(typ.) 9(typ.) us twhwh2 sector erase operation (note 2) 0.7(typ.) 0.7(typ.) 0.7(typ.) sec tvcs vcc setup time (note 1) 50 50 50 us trb recovery time from ry/by 0 0 0 ns tbusy program/erase vaild to ry/by delay 90 90 90 us notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
23 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 29l v040-55r 29l v040-70 29l v040-90 symbol parameter min. max. min. max. min. max. unit twc write cycle time (note 1) 55 70 70 ns tas address setup time 0 0 0 ns tah address hold time 45 45 45 ns tds data setup time 35 35 45 ns tdh data hold time 0 0 0 ns toes output enable setup time 0 0 0 ns tghel read recovery time before write 0 0 0 ns tws we setup time 0 0 0 ns twh we hold time 0 0 0 ns tcp ce pulse width 35 35 35 ns tcph ce pulse width high 30 30 30 ns twhwh1 programming operation(note2) 9(typ.) 9(typ.) 9(typ.) us twhwh2 sector erase operation (note2) 0.7(typ.) 0.7(typ.) 0.7(typ.) sec note: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. ac characteristics ta = -40 o c to 85 o c, vcc = 2.7v~3.6v (ta = 0 o c to 70 o c, vcc = 3.3v 5% for mx29lv004t/b-55r) table 12. alternate ce controlled erase/program operations
24 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 4. command write timing waveform addresses ce oe we din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 3v vih vil vih vil vih vil vih vil vih vil add valid
25 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 automatic programming timing figure 5. automatic programming timing waveform waveform one byte data is programmed. verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. programming comple- tion can be verified by data polling and toggle bit checking after automatic programming starts. device outputs data during programming and data after programming on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) twc address oe ce a0h 555h pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tghwl tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tbusy trb tcs twph tvcs we data ry/by vcc
26 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 6. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify word ok ? yes auto program completed data poll from system increment address last address ? no no
27 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 7. ce controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we oe ce data dq7 pa data polling dout reset ry/by notes: 1.pa=program address, pd=program data, dout=data out, dq7=complement of data written to device. 2.figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
28 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 all data in chip are erased. external erase verification is not required because data is verified automatically by internal control circuit. erasure completion can be veri- fied by data polling and toggle bit checking after auto- matic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) figure 8. automatic chip erase timing waveform automatic chip erase timing waveform twc address oe ce 55h 2aah 555h 10h in progress complete va va notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we data ry/by vcc
29 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 9. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data pall from system auto chip erase completed
30 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 10. automatic sector erase timing waveform sector indicated by a13 to a18 are erased. external erase verify is not required because data are verified automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit check- ing after automatic erase starts. device outputs 0 dur- ing erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic sector erase timing waveform twc address oe ce 55h 2aah sa 30h in progress complete va va notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we data ry/by vcc
31 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 11. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data poll from system auto sector erase completed no last sector to erase yes yes no data=ffh
32 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 12. erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
33 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 13. timing waveform for sector protect/unprotect sector protect =150us sector unprotect =15ms 1us vid vih data sa, a6 a1, a0 ce we oe valid* valid* status valid* sector protect or sector unprotect 40h 60h 60h verify reset note: when sector protect, a6=0, a1=1, a0=0. when sector unprotect, a6=1, a1=1, a0=0.
34 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 14. in-system sector protection algorithm start plscnt=1 first write cycle=60h ye s no reset=vid wait 1us set up sector address write 60h to sector address with a6=0, a1=1, a0=0 verify sector protect : write 40h with a6=0, a1=1, a0=0 wait 150us increment plscnt read from sector address remove vid from reset temporary sector unprotect mode reset plscnt=1 data=01h ye s ye s ye s no no no ? plscnt=25? protect another sector? write reset command sector protect complete device failed
35 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 15. in-system sector unprotection algorithm start plscnt=1 first write cycle=60h ? ye s no reset=vid wait 1us set up first sector address sector unprotect : write 60h with a6=1, a1=1, a0=0 verify sector unprotect write 40h to sector address with a6=1, a1=1, a0=0 wait 50ms increment plscnt read from sector address with a6=1, a1=1, a0=0 remove vid from reset temporary sector unprotect mode set up next sector address all sector protected? ye s data=00h ye s ye s ye s no no no no protect all sectors ? plscnt=1000? last sector verified? write reset command sector unprotect complete device failed
36 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 16. timing waveform for chip unprotection toe data oe we 12v 3v 12v 3v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 sector address a17-a12 f0h notes: twpp1 (write pulse width for sector protect)=100ns min. twpp2 (write pulse width for sector unprotect)=100ns min.
37 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 17. chip unprotection algorithm start protect all sectors plscnt=1 chip unprotect complete data=00h? ye s set oe=a9=vid ce=vil,a6=1 activate we pulse time out 50ms set oe=ce=vil a9=vid,a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device ye s ye s no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
38 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 18. data polling algorithm write operation status read q7~q0 add.=va(1) read q7~q0 add.=va start q7 = data ? q5 = 1 ? q7 = data ? fail pass no no (2) no ye s ye s ye s note : 1.va=valid address for programming 2.q7 should be re-checked even q5="1" because q7 may change simultaneously with q5.
39 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 19. toggle bit alogrithm read q7-q0 read q7-q0 q5= 1? read q7~q0 twice program/erase operation not complete,write reset command program/erase operation complete toggle bit q6= toggle? toggle bit q6 = toggle ? no (note 1) (note 1,2) yes no no yes yes note:1.read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 change to "1". start
40 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 20. data polling timings (during automatic alogrithms) ry/by notes: va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle . tdf tce tacc trc tch toe toeh toh tbusy address ce oe we dq7 q0-q6 status data status data complement complement valid data tr u e va va va high z high z valid data tr u e
41 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 21. toggle bit timing waveforms (during automatic alogrithms) notes: va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tacc trc tch toe toeh tbusy high z toh address ce oe we q6/q2 ry/by valid status (first raed) valid status (second read) (stops toggling) valid data va va va va valid data
42 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 22. reset timing wavform table 13. ac characteristics parameter std description test setup all speed options unit tready1 reset pin low (during automatic algorithms) max 20 us to read or write (see note) tready2 reset pin low (not dur ing automatic max 500 ns algorithms) to read or write (see note) trp reset pulse width (during automatic algorithms) min 500 ns trh reset high time before read(see note) min 50 ns trb ry/by recovery time(to ce, oe go low) min 0 ns note:not 100% tested trh trb tready1 trp trp tready2 ry/by ce, oe reset reset timing not during automatic algorithms reset timing during automatic algorithms ry/by ce, oe reset
43 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 table 14. temporary sector unprotect parameter std. description test setup allspeed options unit tvidr vid rise and fall time (see note) min 500 ns trsp reset setup time for temporary sector unprotect min 4 us note: not 100% tested figure 23. temporary sector unprotect timing diagram reset ce we ry/by tvidr tvidr program or erase command sequence 12v 0 or vcc 0 or vcc trsp figure 24. q6 vs q2 for erase and erase suspend operations notes: the system can use oe or ce to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase erase resume erase complete erase q6 q2
44 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 25. temporary sector unprotect algorithm start reset = vid (note 1) perform erase or program operation reset = vih temporary sector unprotect completed(note 2) note : 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v 2. all previously protected sectors are protected again. operation completed
45 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 figure 26. id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h/00c2h b9h/bah (byte) 22b9h/22bah (word) vid vih vil add a9 add a2-a8 a10-a17 ce oe we add a0 data out data q0-q15 vcc a1 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
46 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 12.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 0.7 15 sec chip erase time 11 sec byte programming time 9 300 us chip programming time 4.5 13.5 sec erase/program cycles 100,000 cycles table 16. latchup characteristics table 15. erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c, 3v. 3.maximum values measured at 25 c, 2.7v.
47 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 ordering information plastic package part no. access time operating current standby current package (ns) max.(ma) max.(ua) mx29lv040tc-55 55 30 5 32 pin tsop mx29lv040tc-70 70 30 5 32 pin tsop mx29lv040tc-90 90 30 5 32 pin tsop mx29lv040qc-55 55 30 5 32 pin plcc mx29lv040qc-70 70 30 5 32 pin plcc mx29lv040qc-90 90 30 5 32 pin plcc mx29lv040ti-70 70 30 5 32 pin tsop mx29lv040ti-90 90 30 5 32 pin tsop MX29LV040QI-70 70 30 5 32 pin plcc mx29lv040qi-90 90 30 5 32 pin plcc
48 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 32-pin plastic leaded chip carrier (plcc) package information
49 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 32-pin plastic tsop
50 p/n:pm0722 mx29lv040 rev. 0.7, jul. 12, 2001 revision history revision no. description page date 0.1 added read cycle time and output enable hold time to read p15 jun/21/2000 operation modify erase/program operation table and timing waveform p17,21,23,25 modify program/erase algorithm flowchart p22,24,26 to added write operation status p32 0.2 modify feature--10,000 minimum erase/program cycles-->100,000-- p1 jul/18/2000 modify general description--even after 10,000 --->100,000 erase-- p1 del package type: 32-pin pdip p1,2 modify ac characteristics twhwh1 9/11(typ.)-->9(typ.) p21 del chip programming time--word mode p45 modify erase/program cycle:10,000-->100,000 p45 0.3 delete unlock bypass command definitions p6 jan/10/2001 delete unlock bypass command sequence p13 modify table 10. dc characteristics vcc=3v 10%-->2.7v to 3.6v p17 0.4 modify timing waveform p25,27,28,30 feb/07/2001 modify automatic programming algorithm flowchart p26 delete figure 21. toggle bit timings(during embedded algorithms) p41 add figure 19. toggle bit alogrithm p39 modify absolute maximum ratings p17 add ordering information--industrial grade p47 0.5 change tbusy spec. from 90ns to 90us p22 mar/07/2001 0.6 correct typing error p22 jun/29/2001 add twpp1/twpp2=100ns p36 to modify package information p48,49 0.7 add 55ns spec p1,19,20,22 jul/12/2001 p23,47
51 mx29lv040 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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